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CS4341A 24-Bit, 192 kHz Stereo DAC with Volume Control
Features
101 dB Dynamic Range -91 dB THD+N +3.3 V or +5 V Power Supply 50 mW with 3. 3V supply Low Clock Jitter Sensitivity Filtered Line Level Outputs On-Chip Digital De-emphasis for 32, 44.1, and 48 kHz ATAPI Mixing Digital Volume Control with Soft Ramp
- 94 dB Attenuation - 1 dB Step Size - Zero Crossing Click-Free Transitions
Description
The CS4341A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4341A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin compatible with the CS4341, as described in section 3.1. These features are ideal for DVD audio players.
Up to 200 kHz Sample Rates Automatic Mode Detection for Sample Rates between 4 and 2 0 0kHz Pin Compatible with the CS4341
ORDERING INFORMATION CS4341A-KS 16-pin SOIC, -10 to 70 C CDB4341A Evaluation Board
SC L/C C LK
SD A/CD IN
AD 0/C S
M U TEC
RST
C ontrol Port Interface
External Mute C ontrol
DAC
Interpolation Filter
Volum e Control
Analog Filter
AO U TA
S e ria l A u dio In terface
SCLK LRC K SD IN
Mixer
Interpolation Filter
Volum e Control
DAC
Analog Filter
AO UTB
/2
M C LK
Preliminary Product Information
Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
AUG `02 DS582PP1 1
CS4341A
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 5 2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 6
3. APPLICATIONS ........................................................................................................................ 7 3.1 Upgrading from the CS4341 to the CS4341A .................................................................... 7 3.2 Sample Rate Range/Operational Mode Detect .................................................................. 7 3.2.1 Auto-Detect Enabled ............................................................................................. 7 3.2.2 Auto-Detect Disabled ............................................................................................ 7 3.3 System Clocking ................................................................................................................ 8 3.4 Digital Interface Format ...................................................................................................... 8 3.5 De-Emphasis Control ......................................................................................................... 9 3.6 Recommended Power-up Sequence ................................................................................. 9 3.7 Popguard(R) Transient Control ........................................................................................... 10 3.7.1 Power-up ............................................................................................................. 10 3.7.2 Power-down ........................................................................................................ 10 3.7.3 Discharge Time ................................................................................................... 10 3.8 Grounding and Power Supply Arrangements .................................................................. 10 3.9 Control Port Interface ....................................................................................................... 11 3.9.1 MAP Auto Increment ........................................................................................... 11 3.9.2 I2C Mode ............................................................................................................. 11 3.9.2a I2C Write .............................................................................................. 11 3.9.2b I2C Read .............................................................................................. 12 3.9.3 SPI Mode ............................................................................................................ 13 3.9.3a SPI Write .............................................................................................. 13 3.10 Memory Address Pointer (MAP) .............................................................................. 14 3.10.1 INCR (Auto Map Increment Enable) ............................................................................ 14 3.10.2 MAP (Memory Address Pointer) .................................................................................. 14 4. REGISTER QUICK REFERENCE .......................................................................................... 14
Contacting Cirrus Logic Support
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IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this docum ent is accurate and reliable. However, the inform ation is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringem ent, and limitation of liability. No responsibility is assumed by Cirrus for the use ofthis information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or im plied under any patents, mask work rights, copyrights , trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not ext nd to other copying such as copying e for general distribution, advertising or promotional purposes, or for creating any work for resale. An export per mit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS M AY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAM AGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
2 Purchase of I2 C com ponents of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I C Patent Rights to use those com ponents in a standard I2 C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are tradem arks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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5. REGISTER DESCRIPTION .................................................................................................... 15 5.1 Mode Control 1 (address 00h) .......................................................................................... 15 5.2 Mode Control 2 (address 01h) .......................................................................................... 15 5.3 Transition and Mixing Control (address 02h).................................................................... 17 5.4 Channel A Volume Control (address 03h) ........................................................................ 20 5.5 Channel B Volume Control (address 04h) ........................................................................ 20 6. CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 21 ANALOG CHARACTERISTICS (CS4341A-KS) ..................................................................... 21 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 23 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................... 26 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 27 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 28 DC ELECTRICAL CHARACTERISTICS ................................................................................ 29 DIGITAL INPUT CHARACTERISTICS ................................................................................... 29 DIGITAL INTERFACE SPECIFICATIONS ............................................................................. 29 THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................... 29 RECOMMENDED OPERATING SPECIFICATION .............................................................. 30 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 30 7. PARAMETER DEFINITIONS .................................................................................................. 31 Total Harmonic Distortion + Noise (THD+N) .......................................................................... 31 Dynamic Range ...................................................................................................................... 31 Interchannel Isolation ............................................................................................................. 31 Interchannel Gain Mismatch ................................................................................................... 31 Gain Error ............................................................................................................................... 31 Gain Drift ................................................................................................................................ 31 8. REFERENCES ........................................................................................................................ 31 9. PACKAGE DIMENSIONS ...................................................................................................... 32
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. DS582PP1 Typical Connection Diagram .......................................................................................... 6 I2S Data ......................................................................................................................... 8 Left Justified up to 24-Bit Data ....................................................................................... 9 Right Justified Data ........................................................................................................ 9 De-Emphasis Curve ....................................................................................................... 9 Control Port Timing, I2C Mode .................................................................................... 12 Control Port Timing, SPI mode .................................................................................... 13 ATAPI Block Diagram .................................................................................................. 19 Output Test Load ......................................................................................................... 22 Maximum Loading ........................................................................................................ 22 Single-Speed Stopband Rejection ............................................................................... 24 Single-Speed Transition Band ..................................................................................... 24 Single-Speed Transition Band (Detail) ......................................................................... 24 Single-Speed Passband Ripple ................................................................................... 24 Double-Speed Stopband Rejection .............................................................................. 24 Double-Speed Transition Band .................................................................................... 24 Double-Speed Transition Band (Detail) ....................................................................... 25 Double-Speed Passband Ripple .................................................................................. 25 Serial Input Timing ....................................................................................................... 26 Control Port Timing - I2C Mode ................................................................................... 27 Control Port Timing - SPI Mode ................................................................................... 28 3
CS4341A
LIST OF TABLES
Table 1. CS4341A Auto-Detect .......................................................................................................... 7 Table 2. CS4341A Mode Select ......................................................................................................... 7 Table 3. Single-Speed Mode Standard Frequencies.......................................................................... 8 Table 4. Double-Speed Mode Standard Frequencies........................................................................ 8 Table 5. Quad-Speed Mode Standard Frequencies........................................................................... 8 Table 7. ATAPI Decode.................................................................................................................... 18 Table 8. Example Digital Volume Settings ....................................................................................... 20
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1. PIN DESCRIPTION
RST SDIN SCLK LRCK MCLK SCL/CCLK SDA/CDIN AD0/CS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MUTEC AOUTA VA AGND AOUTB REF_GND VQ FILT+
Pin Name
RST SDIN SCLK LRCK MCLK SCL/CCLK SDA/CDIN AD0/CS FILT+ VQ REF_GND AOUTR AOUTL AGND VA MUTEC
# 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16
Pin Description
Reset (Input) - Powers down device when enabled. Serial Audio Data (Input) - Input for two's complement serial audio data. Serial Clock (Input) -Serial clock for the serial audio interface. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Input for SPI data. Address Bit / Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode. Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table. Analog Ground (Input) - Ground reference. Power (Input) - Positive power for the analog, digital, control port interface, and serial audio interface sections. Mute Control (Output) - Control signal for optional mute circuit.
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2. TYPICAL CONNECTION DIAGRAM
+ 14 VA 0.1 F 1 F
+3.3V or +5.0V
2 Serial Audio Data Processor 3 4
SDIN SCLK LRCK
CS 4 34 1A
3.3 F AO UT A 15 + 10 k
560
Audio O utput A C RL
MUT EC 5 External Clock M CLK FILT+ VQ
16 9 10 .1 F + 1 F 11 0.1 F + 1 F
O PTIO NAL MUT E CIRCUIT
6 7 MicroControlled Configuration 8
SCL/CCLK SDA/CDIN
REF_G ND 3.3 F 12 AO UT B + 560 Audio O utput B C R L + 560 C= 4 Fs(R L 560) RL
AD0/CS 1 RST AG ND 13
10 k
Figure 1. Typical Connection Diagram
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CS4341A
3. APPLICATIONS 3.1 Upgrading from the CS4341 to the CS4341A
The CS4341A is pin and functionally compatible with all CS4341 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4341, the CS4341A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic speed mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention. The CS4341A does not support an internal serial clock mode or sample rates between 50 kHz and 84 kHz (unless otherwise stated), as does the CS4341.
3.2
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will depend on whether the Auto-Detect Defeat bit is enabled/disabled.
3.2.1
Auto-Detect Enabled
The Auto-Detect feature is enabled by default in the control port register 5.1. In this state, the CS4341A will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (F S) 4kHz - 50kHz 84kHz - 100kHz 170kHz - 200kHz Single Speed Mode Double Speed Mode Quad Speed Mode Table 1. CS4341A Auto-Detect MODE
3.2.2
Auto-Detect Disabled
The Auto-Detect feature can be defeated via the control port register 5.1. In this state, the CS4341A will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must be set appropriately if Fs falls within one of the ranges illustrated in Table 2. Please refer to section 5.1.1 for implementation details. Sample rates outside the specified range for each mode are not supported.
MC1 0 0 1
MC0 0 1 0
Input Sample Rate (F S) 4kHz - 50kHz 50kHz - 100kHz 100kHz - 200kHz Table 2. CS4341A Mode Select
MODE Single Speed Mode Double Speed Mode Quad Speed Mode
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CS4341A
3.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK for each Speed Mode, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
Sample Rate (kHz) 32 44.1 48
256x 8.1920 11.2896 12.2880
384x 12.2880 16.9344 18.4320
MCLK (MHz) 512x 16.3840 22.5792 24.5760
768x 24.5760 33.8688 36.8640
1024x* 32.7680 45.1584 49.1520
Table 3. Single-Speed Mode Standard Frequencies
Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 256x 16.3840 22.5792 24.5760
128x 8.1920 11.2896 12.2880
192x 12.2880 16.9344 18.4320
384x 24.5760 33.8688 36.8640
512x* 32.7680 45.1584 49.1520
Table 4. Double-Speed Mode Standard Frequencies
Sample Rate (kHz) 176.4 192
128x 22.5792 24.5760
MCLK (MHz) 192x 33.8688 36.8640
256x* 45.1584 49.1520
Table 5. Quad-Speed Mode Standard Frequencies
* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).
3.4
Digital Interface Format
The device will accept audio samples in several digital interface formats. The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.
LRC K
Le ft C h a nn el
R ig h t C ha n ne l
SCLK
SD IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LS B
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 2. I2S Data
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CS4341A
LRC K
L e ft C h a n n el
R ig ht C h a n n el
SC LK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 3. Left Justified up to 24-Bit Data
LR C K R ig h t C h a n n e l
L e ft C h a n ne l
S C LK
S D IN
M SB
LSB
+1 +2 +3 +4 +5
-7 -6 -5
-4 -3 -2 -1
M SB
LSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
M SB
3 2 c lo c k s
Figure 4. Right Justified Data
3.5
De-Emphasis Control
The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 5.2.3 for the desired de-emphasis control.
NOTE: De-emphasis is only available in Single-Speed Mode.
G a in dB T 1= 50 s 0dB
T 2 = 15 s -1 0d B
F1 3.183 kH z
F2 F re q u e n cy 10 .61 kH z
Figure 5. De-Emphasis Curve
3.6
Recommended Power-up Sequence
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will remain in a low power state with VQ low. 3. Load the desired register settings while keeping the PDN bit set to 1. 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximatel y 50S when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description of power-up timing.
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CS4341A
3.7 Popguard(R) Transient Control
The CS4341A uses Popguard(R) technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
3.7.1
Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
3.7.2
Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
3.7.3
Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
3.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4341A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimze impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0. 1F, must be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the optimum layout and power supply arrangements.
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3.9 Control Port Interface
The control port is used to load all the internal register settings (see section 5). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I 2C or SPI.
Notes: MCLK must be applied during all I2C communication.
3.9.1
MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
3.9.2
I2C Mode
In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 6 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VA or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.
3.9.2a
I2C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I 2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
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3.9.2b I2C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifications. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see section 8.3) if an I2C read is the first operation performed on the device. 3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
N O TE SDA
0 01 000 AD 0 R /W AC K D AT A 1-8 ACK DA T A 1-8 AC K
SCL S ta rt Stop
N O TE: If operation is a w rite, this byte contains the Me mory Address Pointer, MAP. If operation is a read, this byte contains the data of the register pointed to by th e MAP.
Figure 6. Control Port Timing, I2C Mode
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3.9.3 SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 7 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
3.9.3a
SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.
CS C C LK C H IP ADDRESS C D IN
00 10 00 0 R/W
MAP
MSB
DATA
LSB
byte 1 M AP = M em ory Address Pointe r
byte n
Figure 7. Control Port Timing, SPI mode
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3.10 Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
3.10.1 INCR (AUTO MAP INCREMENT ENABLE) Default = `0' 0 - Disabled 1 - Enabled 3.10.2 MAP (MEMORY ADDRESS POINTER) Default = `000'
4.
0h 1h 2h
REGISTER QUICK REFERENCE
Function
Mode Control 1
DEFAULT
Addr
7
Reserved 0 AMUTE 1 A=B 0 MUTEA 0 MUTEB 0
6
MC1 0 DIF2 0 SOFT 0 VOLA6 0 VOLB6 0
5
MC0 0 DIF1 0 ZERO CROSS 0 VOLA5 0 VOLB5 0
4
Reserved 0 DIF0 0 ATAPI4 0 VOLA4 0 VOLB4 0
3
Reserved 0 DEM1 0 ATAPI3 0 VOLA3 0 VOLB3 0
2
AUTOD 0 DEM1 0 ATAPI2 0 VOLA2 0 VOLB2 0
1
0 POR 1 ATAPI1 0 VOLA1 0 VOLB1 0
0
0 PDN 1 ATAPI0 0 VOLA0 0 VOLB0 0
MCLKDIV Reserved
Mode Control 2
DEFAULT
Transition and Mixing Control
DEFAULT
3h
Channel A Volume Control
DEFAULT
4h
Channel B Volume Control
DEFAULT
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5. REGISTER DESCRIPTION
NOTE: All registers are read/write in I2C mode and write only in SPI mode, unless otherwise stated.
5.1
MODE CONTROL 1 (ADDRESS 00H)
6 MC1 0 5 MC0 0 4 Reserved 0 3 Reserved 0 2 AUTOD 0 1 MCLKDIV 0 0 Reserved 0
7 Reserved 0
5.1.1 SPEED MODE CONTROL (MC) Default = 00 00 - Single-Speed Mode 01 - Double-Speed Mode 10 - Quad-Speed Mode
BIT 5-6
The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These bits are ignored if the auto-detect defeat is disabled (AUTOD = 0). 5.1.2 AUTO-DETECT DEFEAT (AUTOD) Default = 0 0 - Disabled 1 - Enabled The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from 100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section 5.1.1) if the auto-detect feature is defeated. 5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV) Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
BIT 1 BIT 2
5.2
MODE CONTROL 2 (ADDRESS 01H)
6 DIF2 0 5 DIF1 0 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 POR 1 0 PDN 1
7 AMUTE 1
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5.2.1 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similiar to volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. 5.2.2 DIGITAL INTERFACE FORMAT (DIF)
BIT 4-6 BIT 7
Default = 000 - Format 0 (I2S, up to 24-bit data) Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 2-4.
DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION I2S, up to 24-bit data Identical to Format 1 Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 Format 1 1 2 3 4 5 6 1 FIGURE 2 2 3 4 4 4 4 2
Table 6. Digital Interface Format 5.2.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3 Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Implementation of the standard 15s/50s digital de-emphasis filter response, Figure 5, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is only available in Single-Speed Mode.
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5.2.4 POPGUARD (R) TRANSIENT CONTROL (POR) Default = 1 0 - Disabled 1 - Enabled Function: The PopGuard(R) Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-down. Please refer to section 3.7 for implementation details. 5.2.5 POWER DOWN (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The device will enter a low-power state when this function is enabled. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation can occur. The contents of the control registers are retained in this mode.
BIT 0 BIT 1
5.3
TRANSITION AND MIXING CONTROL (ADDRESS 02H)
7 A=B 0 6 SZC1 1 5 SZC0 0 4 ATAPI4 0 3 ATAPI3 1
BIT 7
2 ATAPI2 0
1 ATAPI1 0
0 ATAPI0 1
5.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) Default = 0 0 - Disabled 1 - Enabled
Fucntion: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
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5.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC) Default = 10 00 - Immediate Changes 01 - Changes On Zero Crossings 10 - Soft Ramped Changes 11 - Soft Ramped Changes On Zero Crossings Fucntion: Immediate Changes When Immediate Changes is selected all level changes will take effect immediately in one step. Changes On Zero Crossings Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independenttly monitored and implemented for each channel. Soft Ramped Changes Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Soft Ramped Changes on Zero Crossings Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is indepently monitored and implemented for each channel. 5.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-4 Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo) Fucntion: The CS4341A implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 7 and Figure 8 for additional information. ATAPI4 0 0 0 0 0 0 0 0 0 0 ATAPI3 0 0 0 0 0 0 0 0 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 ATAPI1 0 0 1 1 0 0 1 1 0 0 ATAPI0 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR
BIT 5-6
Table 7. ATAPI Decode
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ATAPI4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTB bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
Table 7. ATAPI Decode (Continued)
L eft C han nel A ud io D ata
A C h an nel V olum e C o ntro l
M U TE
Ao utA
R ig ht C ha nne l A ud io D ata
B C h an ne l V o lu m e C o ntro l
M U TE
Ao utB
Figure 8. ATAPI Block Diagram
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5.4 5.5 CHANNEL A VOLUME CONTROL (ADDRESS 03H) CHANNEL B VOLUME CONTROL (ADDRESS 04H)
7 MUTEx 0 6 VOLx6 0
BIT 7
5 VOLx5 0
4 VOLx4 0
3 VOLx3 0
2 VOLx2 0
1 VOLx1 0
0 VOLx0 0
5.5.1 MUTE (MUTE)
Default = 0 0 - Disabled 1 - Enabled Fucntion: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels. 5.5.2 VOLUME (VOLx)
BIT 0-6
Default = 0 dB (No Attenuation) Function: The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit. Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB
Table 8. example Digital Volume Settings
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6. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (CS4341A-KS) (Test conditions (unless otherwise specified):
Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R L = 10k, C L = 10 pF (see Figure 9). Typical performance characteristics are derived from measurements taken at TA = 25 C, VA = 5.0V and 3.3V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) VA = 5.0V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit Fs = 48kHz
(Note 1)
VA = 3.3V Max Min Typ Max Unit
Min
Typ
unweighted A-Weighted unweighted A-Weighted
(Note 1)
92 95 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-85 -
88 91 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-88 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96kHz
(Note 1)
Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
unweighted A-Weighted unweighted A-Weighted
(Note 1)
92 95 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-85 -
88 91 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-88 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 192kHz
(Note 1)
Quad-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
unweighted A-Weighted unweighted A-Weighted
(Note 1)
92 95 -
98 101 92 95 -91 -78 -38 -90 -72 -32
-85 -
88 91 -
94 97 92 95 -94 -74 -34 -91 -72 -32
-88 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
0 dB -20 dB -60 dB 0 dB -20 dB -60 dB
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ANALOG CHARACTERISTICS (CS4341A-KS) (Continued)
Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance
(Note 2) (Note 2)
Symbol
Min 0.6*VA -
Typ 102 0.1 100 0.7*VA 100 3 100
Max 0.8*VA -
Units dB dB ppm/C Vpp k pF
RL CL
-
Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Refer to Figure 10.
.
125 C a p a citive L o a d -- C L (p F )
3.3 F A O UT x + V ou t R L C L
100 75 50 25 S a fe O p e ra tin g R e g io n
AG N D
2 .5 3
5
10
15
20
R e s is tiv e L o a d -- R L (k )
Figure 9. Output Test Load
Figure 10. Maximum Loading
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The
filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter Single-Speed Mode - (4kHz to 50kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation De-emphasis Error (Relative to 1 kHz)
(Note 4) (Note 3)
Min
Typ
Max
Unit
0 0 -0.02 0.5465 50 -
9/Fs 0.36/Fs -
0.4535 0.4998 +0.08 +0.2/-0.1 +0.05/-0.14 +0/-0.22
Fs Fs dB Fs dB s s dB dB dB
0 - 20 kHz Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz
Double-Speed Mode - (50kHz to 100kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation Quad-Speed Mode - (100kHz to 200kHz sample rates) Frequency Response 10 Hz to 20 kHz Group Delay -1 3/Fs 0 dB s 0 - 40 kHz 0 - 20 kHz
(Note 3)
0 0 -0.06 0.577 55 -
4/Fs 1.39/Fs 0.23/Fs
0.4621 0.4982 +0.2 -
Fs Fs dB Fs dB s s s
Notes: 3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 4. De-emphasis is only available in Single-Speed Mode.
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Figure 11. Single-Speed Stopband Rejection
Figure 12. Single-Speed Transition Band
Figure 13. Single-Speed Transition Band (Detail)
Figure 14. Single-Speed Passband Ripple
Figure 15. Double-Speed Stopband Rejection
Figure 16. Double-Speed Transition Band
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Figure 17. Double-Speed Transition Band (Detail)
Figure 18. Double-Speed Passband Ripple
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CS4341A
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs Symbol Min 1.024 45 4 50 100 40 tsclkl tsclkh MCLKDIV Disabled MCLKDIV Enabled SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tslrd tslrs tsdlrs tsdh 20 20 20 20 20 20 Max 51.2 55 50 100 200 60 MCLK ----------------2 MCLK ----------------4
Units MHz % kHz kHz kHz % ns ns Hz Hz ns ns ns ns
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Frequency
-
LR C K t t slrd slrs t sclkl t sclkh
S C LK t sdlrs
t
sdh
S D IN
Figure 19. Serial Input Timing
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SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Inputs: Logic
0 = AGND, Logic 1 = VA) Parameter I2C Mode fscl tirs tbuf thdst tlow thigh tsust
(Note 5)
Symbol
Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7
Max 100 1 300 -
Unit kHz ns s s s s s s ns s ns s
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition
thdd tsud trc, trc tfc, tfc tsusp
Notes: 5. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t S to p irs S t a rt R e p e a te d S ta rt t rd t fd S to p
SDA t b uf t h dst t h ig h t h ds t t fc t s u sp
SCL t t t sud t ack t s u st t rc
lo w
h dd
Figure 20. Control Port Timing - I2C Mode
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SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
(Note 7) (Note 8) (Note 8) (Note 6)
(Continued) Max 6 100 100 Unit MHz ns ns s ns ns ns ns ns ns ns
Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2
Min 500 500 1.0 20 66 66 40 15 -
Notes: 6. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 7. Data must be held for sufficient time to bridge the transition time of CCLK. 8. For fsclk < 1 MHz.
RST
t srs
CS t spi t css C C LK t r2 C D IN t f2 t scl t sch t csh
t dsu t dh
Figure 21. Control Port Timing - SPI Mode
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DC ELECTRICAL CHARACTERISTICS
Parameters Normal Operation (Note 9) Power Supply Current Power Dissipation Power-down Mode (Note 10) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 11) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage MUTEC High-Level Output Voltage Maximum MUTEC Drive Current 1 kHz 60 Hz PSRR 60 40 0.5*VA 250 0.01 VA 250 0.01 0 VA 3 dB dB V VA = 5.0V VA = 3.3V VA = 5.0V VA = 3.3V IA 60 35 0.3 0.1 A A mW mW VA = 5.0V VA = 3.3V VA = 5.0V VA = 3.3V IA 18 15 90 50 25 20 125 100 mA mA mW mW (AGND = 0V; all voltages with respect to AGND.) Symbol Min Typ Max Units
k
mA V
k
mA V V mA
DIGITAL INPUT CHARACTERISTICS (AGND = 0V; all voltages with respect to AGND.)
Parameters Input Leakage Current Input Capacitance Symbol Iin Min Typ 8 Max 10 Units A pF
DIGITAL INTERFACE SPECIFICATIONS
Parameters Interface Voltage Supply = 3.3V or 5.0V High-Level Input Voltage Low-Level Input Voltage
(GND = 0 V; all voltages with respect to GND.) Symbol VIH VIL Min 2.0 Max 0.8 Units V V
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance Ambient Operating Temperature (Power Applied) Symbol JA TA Min -10 Typ 125 Max +70 Units C/Watt C
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RECOMMENDED OPERATING SPECIFICATION
Parameters DC Power Supply Analog VA 2.7 4.5 3.3 5 3.6 5.5 V V Symbol Min Typ Max Units
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameters DC Power Supply Input Current Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature
(Note 12)
Symbol VA Iin VIND TA Tstg
Min -0.3 -0.3 -55 -65
Max 6.0 10 VA+0.4 125 150
Units V mA V C C
Notes: 9. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 10. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 11. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR. 12. Any pin except supplies.
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7. PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
Total Harmonic Distortion + Noise (THD+N)
8.
REFERENCES
1) CDB4341A Evaluation Board Datasheet 2) "The I2C Bus Specification: Version 2.1" Philips Semiconductors, January 2000. http://www.semiconductors.philips.com
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9. PACKAGE DIMENSIONS
16L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.386 0.150 0.040 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8 JEDEC # : MS-012
MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8
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